How much time do you have to answer the data request, and how long does it take to prefetch for the next one? If the prefetch time is short, I would reverse your priority on your interrupts - this keeps the buffer filled for the data request interrupt.
Otherwise there isn't a clean way to do what you want bare-metal - this is what Operating Systems are for. If you are in an OS, the data request interrupt routine can request a signal from the prefetch interrupt routine and return from interrupt and wait for the data request interrupt routine to send a signal that it has completed a block.
Bare-metal, you could try having the prefetch routine call the data request interrupt after each buffer is ready. The DRIR then does a series of checks when it wakes up
- Was I woken by a Data Request?
- yes: Do I have data to send?
- yes: Send data, clear interrupt request, return from interrupt
- no: Increment "blocks needed" counter by 1, clear interrupt request, return from interrupt
- no: must have been woken by a Prefetch complete, is "blocks needed" zero?
- yes: buffer has data, but not needed yet, return
- no: Send 1 block of data, decrement "blocks needed" until it hits zero or buffer is empty, return
- yes: Do I have data to send?
There isn't any guarantee you will get the data out in time, but at least this way there's a chance for the lower priority interrupt to finish.
BTW, I don't think the NVIC can force a currently-executing interrupt to stop for a different higher-priority one. The priorities really matter when the interrupts occur at the same time (or occur when interrupts are already masked, ie when servicing another interrupt).
Many operating systems provide a two-step interrupt process where the direct interrupt routine is minimal as possible to clear the interrupt, and it notifies a separate interrupt thread to handle the longer, detailed parts of the request. See http://en.wikipedia.org/wiki/Interrupt_handler
Since the direct interrupt routine is small&fast, it allows for priorities to be assigned to the respective interrupt threads to control execution order.