GCC4 - ARMv5 register allocations

Question

Is there a way to ask GCC to generate code that uses the registers in a way unlike the standard ABI for that architecture.

I am using an ARMv4 chip (LPC2000) and I need my fast interrupts to be faster.

I have a FIQ routine, but I have to store r0..r7 on the stack, this seems pointless as FIQ mode as it's own bank of registers R8..r15. I want to use those instead and save 16 instruction cycles used to push and pop stuff off the stack.

Before anybody states the obvious: re-write the FIQ handler in assembly language, yes I know I can do that, This question is more specific.

Is there a #pragma or __attribute__ or switch that tells GCC4 to change the order it allocates registers within a function?

Answer 1

A. This should be correctly optimized away when you declare the function with the interrupt pragma:

void f () __attribute__ ((interrupt ("FIQ")));

Source: http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html#Function-Attributes

B. But I find an open bug report that this currently does not optimize away the push/pop of the relevant registers. The bug report has been classified as a 'missed optimization' and has been open since being confirmed in June 2011.

Source: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48429