Memory fencing at compiler level and hardware level

Question

I read about memory fencing here... And I need a little clarification about it

asm volatile ("" : : : "memory")

This provides a compiler level memory fence and processor can still do reordering when this is used.

Is there anyway I can achieve both compiler level fencing and processor level fencing with a similar instruction?

I came across,

asm volatile("sfence" : : : "memory")

What does this do? Does it provide only compiler level store fencing?

Any inputs on this will be very helpful.

Thanks

Answer 1

They perform two conceptually-related but functionally different actions:

asm volatile ("" : : : "memory")

tells the compiler to not reorder memory accesses around that point (which it otherwise is free to do for optimization purposes), so that you can be assured that loads and stores which were written into your code are finished by the time you hit that point in the code.

asm volatile("sfence" : : : "memory")

is an actual intel-family cpu command (sfence), which tells the hardware not to reorder stores (there's also lfence and mfence hardware instructions) for purposes of optimization; adding the "memory" constraint tells the compiler to not reorder memory accesses as well.

Wikipedia has a decent treatment of the subject (http://en.wikipedia.org/wiki/Memory_barrier); if you want a bit more in-depth, you should check out the intel programmer's manual (http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html/)