Initialization of array error in Verilog

Question

When I initialize an array sbox, I am getting syntax errors. Please help me out.

  reg  [7:0] sbox[15:0];
sbox = '{
 8'h63, 8'h7c, 8'h77, 8'h7b,
 8'hf2, 8'h6b, 8'h6f, 8'hc5,
 8'h30, 8'h01, 8'h67, 8'h2b,
 8'hfe, 8'hd7, 8'hab, 8'h76
};

This is actually sbox. Error it was showing:

near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER

I was using modelsim simulator

Answer 1

The syntax you are using for the array assignment is only valid in SystemVerilog, not Verilog.

So your compiler needs to support this, and you need to tell the compiler that the file is SystemVerilog. Most compilers (including modelsim) will assume the file type based on the extension, e.g. .v == Verilog and .sv == SystemVerilog, while others required a switch.

In addition, as pointed out in the answer from toolic, you need to place the assignment in an initial block, or you could combine the declaration with the assignment, like this:

reg [7:0] sbox[15:0] = '{
        8'h63, 8'h7c, 8'h77, 8'h7b,
        8'hf2, 8'h6b, 8'h6f, 8'hc5,
        8'h30, 8'h01, 8'h67, 8'h2b,
        8'hfe, 8'hd7, 8'hab, 8'h76
};

Answer 2

The assignment should be inside an initial or always block:

module tb;

reg [7:0] sbox[15:0];

initial begin
    sbox = '{
        8'h63, 8'h7c, 8'h77, 8'h7b,
        8'hf2, 8'h6b, 8'h6f, 8'hc5,
        8'h30, 8'h01, 8'h67, 8'h2b,
        8'hfe, 8'hd7, 8'hab, 8'h76
    };
end

endmodule