Too pull this off, first make dual-edge,dual-clock flip-flop. Start off with a dual clock D flip-flop Patent US6320442 B1. Now substitute the sub flip-flops with dual edge D flip-flops Patent US5793236 A or Patent US5327019 A. Each patent has diagrams of the circuit design.
With the custom flop, create a small pipeline sampling the history of the clocks. Look for a zero to one transition.
Example:
wire [1:0] historyA, historyB;
// dualedge_dualclock_dff ( output Q, input D, clkA, clkB, rst_n)
dualedge_dualclock_dff dedc_histA1( .Q(historyA[1]), .D(historyA[0]), .* );
dualedge_dualclock_dff dedc_histA0( .Q(historyA[0]), .D(clkA), .* );
dualedge_dualclock_dff dedc_histB1( .Q(historyB[1]), .D(historyB[0]), .* );
dualedge_dualclock_dff dedc_histB0( .Q(historyB[0]), .D(clkB), .* );
wire dual_posedge_match = ({historyA,historyB} == 4'b0101);
Dual-edge flops and dual-clock flops are not common design practices. Excessive timing analysis will be needed and tools might complain about the cell. Plus, steps need to be taken for patent uses compliance with the law.