I have developed testbench using UVM methodology in system verilog for my whole system DUT. I have a VIP procured, which is in VMM methodology in system verilog. How do I integrate this VIP (in VMM) into my UVM testbench?

Thanks.

有帮助吗?

解决方案

  1. Ask your VIP provider for the UVM version of the VIP.
  2. Ask your simulation vendor for a VMM to UVM integration package.
许可以下: CC-BY-SA归因
不隶属于 StackOverflow
scroll top