문제

I have developed testbench using UVM methodology in system verilog for my whole system DUT. I have a VIP procured, which is in VMM methodology in system verilog. How do I integrate this VIP (in VMM) into my UVM testbench?

Thanks.

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해결책

  1. Ask your VIP provider for the UVM version of the VIP.
  2. Ask your simulation vendor for a VMM to UVM integration package.
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