How does VHDL deal with overflow?

Question

I am working on a design where I believe some overflow may be occurring that I need to deal with. In order to solve my problem I need to understand how VHDL deals with binary overflow. Some sample code is below.

signal temp   : std_logic_vector (7 downto 0) := "11111111"; 
signal temp_2 : std_logic_vector (7 downto 0) := "11111111";
signal result : std_logic_vector (8 downto 0) := "000000000";

result <= temp + temp_2 ;

Obviously this does not have the relevant libraries called, but it gives an idea of the code I am working with. My question is this : how does this binary addition work (temp + temp_2) i.e what would the signal result be after running this code? Right now, I am getting a error in the compilation because result is 9 bits and its expecting 8 bits. Any explanation of exactly how this binary addition works would be very helpful!

Answer 1

VHDL is strongly typed. Any time you assign a signal, you need to match types and widths.

For types: You cannot assign an integer typed signal to a std_logic_vector signal, the compiler will throw an error. You must convert the integer to std_logic_vector first.

For widths: You need to always match width assignments perfectly. In your case, the tool is mad at you because you're assigning something that is 8 bits wide to the signal result which is 9 bits wide.

In order to accomplish what you want, you must use sign-extension. Are you inputs signed or unsigned? If they are unsigned, just add a '0' in the most significant bit position. If they are signed, you must determine the sign of bit position 7, then extend that into bit position 8.

Here's how you could do in both cases:

temp_extended_unsigned <= '0' & temp(7 downto 0);
temp_extended_signed   <= temp(7) & temp(7 downto 0);

temp_2_extended_unsigned <= '0' & temp_2(7 downto 0);
temp_2_extended_signed   <= temp_2(7) & temp_2(7 downto 0);

result <= temp_extended_unsigned + temp_2_extended_unsigned; -- unsigned case
result <= temp_extended_signed   + temp_2_extended_signed; -- signed case

Note that adding 1 bit position works fine for addition, but what about multiplication? You must consider your operation to be performed... multiplying two 8 bit wide vectors will produce a result that is 16 bits wide, so you must do sign-extension on the upper 8 bits in that example.