Fetch Microoperations for CALL

Question

I am trying to understand how the fetch cycle would be written in micro-operations for a CALL instruction of 32 bits were to be fetched by the cpu.

MAR is 16 bits wide
MDR is 8 bits wide
PC is 16 bits wide
IR is 16 bits wide
Temp registers are 16 bits wide

My question stems from the fact that the instruction is 32 bits, the high 16 bits represent the opcode, and the low 16 bits represent the destination address that we are jumping to.

The fetch cycle is like such:

MAR <- PC

MDR <- M(MAR)

IR <- MDR opcode

MAR <- MDR address

PC <- PC + 1

Since MDR is only 8 bits wide, how do we adjust this fetch cycle to account for the entire opcode, and address which are 16 bits wide each?

Answer 1

I'm assuming little endian architecture for dealing with memory. Also I assume one of the registers is called SP and is a stack pointer, growing downwards. High part and low part of PC, TEMP and IR can be accessed independently.

/* FETCH................ */
MAR <- PC
PC <- PC+1
MDR <- M(MAR)  ;low 8 bits of opcode
IRlow <- MDR

MAR <- PC
PC <- PC+1
MDR <- M(MAR)  ;high 8 bits of opcode
IRhigh <- MDR

/* DECODE AND EXECUTE................ */
if MDR is opcode for CALL...
MAR <- PC
PC <- PC+1
MDR <- M(MAR)  ;low 8 bits of destination
TEMPlow <- MDR

MAR <- PC
PC <- PC+1
MDR <- M(MAR)  ;high 8 bits of destination
TEMPhigh <- MDR

SP <- SP-1
MAR <- SP
MDR <- PChigh
M(MAR) <- MDR  ;store hi part of next instruction in stack

SP <- SP-1
MAR <- SP
MDR <- PClow
M(MAR) <- MDR  ;store low part of next instruction in stack

PC <- TEMP    ;update PC to jump to the called address