I'm assuming little endian architecture for dealing with memory. Also I assume one of the registers is called SP and is a stack pointer, growing downwards. High part and low part of PC, TEMP and IR can be accessed independently.
/* FETCH................ */
MAR <- PC
PC <- PC+1
MDR <- M(MAR) ;low 8 bits of opcode
IRlow <- MDR
MAR <- PC
PC <- PC+1
MDR <- M(MAR) ;high 8 bits of opcode
IRhigh <- MDR
/* DECODE AND EXECUTE................ */
if MDR is opcode for CALL...
MAR <- PC
PC <- PC+1
MDR <- M(MAR) ;low 8 bits of destination
TEMPlow <- MDR
MAR <- PC
PC <- PC+1
MDR <- M(MAR) ;high 8 bits of destination
TEMPhigh <- MDR
SP <- SP-1
MAR <- SP
MDR <- PChigh
M(MAR) <- MDR ;store hi part of next instruction in stack
SP <- SP-1
MAR <- SP
MDR <- PClow
M(MAR) <- MDR ;store low part of next instruction in stack
PC <- TEMP ;update PC to jump to the called address