Problems Accessing the Cellular RAM on Nexys 3 FPGA

Question

I am trying to use the Cellular RAM on the Nexys 3 FPGA. As of now I have an 8 bit .wav file stored in the RAM (I have verified that the RAM is functioning multiple times with Adept). Other parts of the FPGA design are functioning as I am getting other outputs, but no data. I am at a loss for why this is occurring because the data should be stored in byte format so that is how it should be accessed and then processed.

Below are snippets of my code used to access and the read in the data from the RAM. The Memory Access program accesses the RAM and then returns two 8-bit numbers for the the other processing that occurs (which is functioning now).

--Toplevel Buses    
MemAdr              :    out std_logic_vector (26 downto 1); -- memory address
MemDB               : in     std_logic_vector (15 downto 0)  -- memory address

--Memory Access
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity mem_access is

    port(
    o_datain_r        :    out std_logic_vector (7 downto 0); -- 8 bit from memory
    o_datain_l        :    out std_logic_vector (7 downto 0); -- 8 bit from memory
    o_addressbus      :    out std_logic_vector (26 downto 1);

    i_databus         : in     std_logic_vector (15 downto 0);
    i_sampleclock     : in     std_logic;
    i_clock           : in     std_logic;
    i_reset           : in     std_logic    

    );
end mem_access;

architecture Behavioral of mem_access is

    signal clockpulses       : integer ;
    signal counter           : std_logic_vector (24 downto 0);
    signal channel_select    : std_logic; 

begin

--*******************************************************--
data_access: process (i_sampleclock, i_reset, clockpulses)
begin
    if (i_reset = '1') then
        channel_select <= '0';
        o_addressbus   <= (others => '0');
        o_datain_r     <= X"00";
        o_datain_l     <= X"00";
        counter        <= (others => '0');

    elsif (clockpulses = 0) then
        channel_select <= '0';
        o_addressbus   <= channel_select & counter;

    elsif (clockpulses = 75) then
        o_datain_r     <= i_databus (7 downto 0);

    elsif (clockpulses = 100) then
        channel_select <= '1';
        o_addressbus   <= channel_select & counter;

    elsif (clockpulses = 175) then  
        channel_select <= '0';
        o_addressbus   <= channel_select & counter;

    elsif (clockpulses = 275) then 
        o_datain_l     <= i_databus (7 downto 0);

    elsif (rising_edge(i_sampleclock)) then
        counter <= counter + '1';

    elsif (counter = "1111111111111111111111111") then
        counter <= (others => '0');

    end if;

end process;
--*******************************************************--
clkpulses_counter: process (i_clock, i_reset, i_sampleclock)
begin

    if (i_reset = '1') then 
        clockpulses <= 0;
    elsif (rising_edge(i_clock)) then
        clockpulses <= clockpulses + 1;     
    end if;

    if (rising_edge(i_sampleclock)) then
        clockpulses <= 0;
    end if;

end process;
--*******************************************************--

end Behavioral;

Answer 1

I was unable to get this to work. This is likely because I was unable to find the correct way to enable the Cellular RAM. For future work, make sure to research all of the enable pins necessary to make the Cellular RAM work because it is an external component.