The standard
package with bit
also has a bit_vector
, so if the interface
can be changed to use vector instead of single bits, then the code can be
written for VHDL-2002 as:
ENTITY cc IS
PORT ( s : IN BIT;
x : IN BIT_VECTOR(0 TO 9);
y : IN BIT_VECTOR(0 TO 9);
m : OUT BIT_VECTOR(0 TO 9));
END cc;
ARCHITECTURE cc_logic OF cc IS
BEGIN
loop_gen : FOR idx IN m'RANGE GENERATE
m(idx) <= ((NOT s) XOR x(idx)) XNOR (s OR y(idx));
end generate;
END cc_logic;
Note that NOT(s)
, was changed to (NOT s)
since assumption is that it is the
intention, and the logical operation when doing outer XOR
is equivalent.
The architecture may also be written without the generate loop doing:
ARCHITECTURE cc_logic OF cc IS
SIGNAL s_vec : BIT_VECTOR(0 to 9);
BEGIN
s_vec <= (OTHERS => s);
m <= ((NOT s_vec) XOR x) XNOR (s_vec OR y);
END cc_logic;
And if VHDL-2008 is supported in the used tools, then you can reduce it even more with:
ARCHITECTURE cc_logic OF cc IS
BEGIN
m <= ((NOT s) XOR x) XNOR (s OR y);
END cc_logic;
Finally, you may consider using std_logic
and std_logic_vector
instead of
bit
and bit_vector
, since the additional states in std_logic
makes
simulation more accurate when having unknown input data.