VHDL simple optimization

Question

I have the following code and I am trying if possible to make it more professional, by using loops for example.

ENTITY cc IS
    PORT ( s, x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, y0, y1, y2, y3, y4, y5, y6, y7, y8, y9    : IN    BIT;
           m0, m1, m2, m3, m4, m5, m6, m7, m8, m9                                               : OUT   BIT );
END cc;

ARCHITECTURE cc_logic OF cc IS
BEGIN
    m0 <= (NOT(s) XOR x0) XNOR (s OR y0) ;
    m1 <= (NOT(s) XOR x1) XNOR (s OR y1) ;
    m2 <= (NOT(s) XOR x2) XNOR (s OR y2) ;
    m3 <= (NOT(s) XOR x3) XNOR (s OR y3) ;
    m4 <= (NOT(s) XOR x4) XNOR (s OR y4) ;
    m5 <= (NOT(s) XOR x5) XNOR (s OR y5) ;
    m6 <= (NOT(s) XOR x6) XNOR (s OR y6) ;
    m7 <= (NOT(s) XOR x7) XNOR (s OR y7) ;
    m8 <= (NOT(s) XOR x8) XNOR (s OR y8) ;
    m9 <= (NOT(s) XOR x9) XNOR (s OR y9) ;
END cc_logic ;

Is this possible?

Answer 1

The standard package with bit also has a bit_vector, so if the interface can be changed to use vector instead of single bits, then the code can be written for VHDL-2002 as:

ENTITY cc IS
    PORT ( s : IN  BIT;
           x : IN  BIT_VECTOR(0 TO 9);
           y : IN  BIT_VECTOR(0 TO 9);
           m : OUT BIT_VECTOR(0 TO 9));
END cc;

ARCHITECTURE cc_logic OF cc IS
BEGIN
  loop_gen : FOR idx IN m'RANGE GENERATE
    m(idx) <= ((NOT s) XOR x(idx)) XNOR (s OR y(idx));
  end generate;
END cc_logic;

Note that NOT(s), was changed to (NOT s) since assumption is that it is the intention, and the logical operation when doing outer XOR is equivalent.

The architecture may also be written without the generate loop doing:

ARCHITECTURE cc_logic OF cc IS
  SIGNAL s_vec : BIT_VECTOR(0 to 9);
BEGIN
  s_vec <= (OTHERS => s);
  m <= ((NOT s_vec) XOR x) XNOR (s_vec OR y);
END cc_logic;

And if VHDL-2008 is supported in the used tools, then you can reduce it even more with:

ARCHITECTURE cc_logic OF cc IS
BEGIN
  m <= ((NOT s) XOR x) XNOR (s OR y);
END cc_logic;

Finally, you may consider using std_logic and std_logic_vector instead of bit and bit_vector, since the additional states in std_logic makes simulation more accurate when having unknown input data.