I'm guessing that somewhere in your design there is something like the following:
module upper_module;
// ...
`include "register.v"
// ...
endmoudle
This would create a nested module. To fix it, move the `include
line above module
or below endmodule
.
Technically nested modules are part of SystemVerilog (see IEEE Std 1800-2005 § 19.6 Nested modules & IEEE Std 1800-2012 § 23.4 Nested modules), however may vendors have not implemented this feature.
FYI: or posedge e
shouldn't be there. Synchronous logic should be a edged clock and zero to two async resets, where the async reset assigns the flop(s) to a content.