Found 'module' keyword inside a module before the 'endmodule'

Question

I am working on a simple cpu with a register in system verilog as follows:

module register(
input clk, e,
input [7:0]in,
output reg [7:0]out
);

always@(posedge clk or posedge e)
begin
    if(e == 1)
        out <= in;
    else
        out <= out; 
end
endmodule

When I compile everything, I get the following errors:

Error-[USVSNM] Unsupported System Verilog construct
register.v, 1
lm2
Found 'module' keyword inside a module before the 'endmodule'. Nested 
modules are not supported.


Error-[SE] Syntax error
Following verilog source has syntax error :
"register.v", 2: token is 'input'
input clk, e,
           ^

I'm scratching my head on this one. I only see module declared once, and I don't see anything wrong with my syntax. Any help is appreciated!

Answer 1

I'm guessing that somewhere in your design there is something like the following:

module upper_module;
// ...
`include "register.v"
// ...
endmoudle

This would create a nested module. To fix it, move the `include line above module or below endmodule.

Technically nested modules are part of SystemVerilog (see IEEE Std 1800-2005 § 19.6 Nested modules & IEEE Std 1800-2012 § 23.4 Nested modules), however may vendors have not implemented this feature.

---

FYI: or posedge e shouldn't be there. Synchronous logic should be a edged clock and zero to two async resets, where the async reset assigns the flop(s) to a content.