Identifying a start of a frame

Question

I have implemented a HDMI Transmitter and receiver on a Atlys Spartan 6 board. Its working properly. I am using 1080p @ 60Hz. The board takes a one pixel, decodes it, encode it back and send it to the monitor.

Now i need to identify the start of a new frame. Because i want to draw a square on the middle of the screen (using the FPGA). I thought when both HSYNC and VSYNC are '1' that implies a start of a new frame. But it seems that is not the case.

Can anyone tell me abot how to identify the start of new HDMI frame?

Thank you!

Answer 1

The start of a new frame is after VSYNC has changed to '1' and later (or at the same time, it depends on your data source) HSYNC has also changed to '1'.

You need to detect edges. In VHDL, a process like this:

process(clk)
   variable last_hsync, last_vsync, got_vsync : std_logic;
begin
   if rising_edge(clk) then
       if vsync = '1' and last_vsync = '0' then
           got_vsync := '1';
       end if;
       if got_vsync and hsync = '1' and last_hsync = '0' then
           first_pixel <= '1';
       end if;
       last_vsync := vsync;
       last_hsync := hsync;
    end if;
end process;

That may flag a false start of frame if you come up mid-frame - you may need some extra state to manage those cases, if it matters, but that's system dependent.