The start of a new frame is after VSYNC has changed to '1' and later (or at the same time, it depends on your data source) HSYNC has also changed to '1'.
You need to detect edges. In VHDL, a process like this:
process(clk)
variable last_hsync, last_vsync, got_vsync : std_logic;
begin
if rising_edge(clk) then
if vsync = '1' and last_vsync = '0' then
got_vsync := '1';
end if;
if got_vsync and hsync = '1' and last_hsync = '0' then
first_pixel <= '1';
end if;
last_vsync := vsync;
last_hsync := hsync;
end if;
end process;
That may flag a false start of frame if you come up mid-frame - you may need some extra state to manage those cases, if it matters, but that's system dependent.