Question

Here is some Verilog code that I'm trying to run in Modelsim.

parameter Data_width = 8; //DATA SIZE
input CLK, RST;
input [Data _width-1:0] D;

When I try to compile it, the compiler complains about Data_width in the last line, saying that it expects an identifier. I could hardcode the number in there to get rid of the problem, but I would prefer to use a variable in case I want to change it so I don't have to change it. How can this be fixed?

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Solution

The code you posted has a space between Data and _width in the last line. Change it to:

input [Data_width-1:0] D;
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