rising_edge function avoids "latch warnings"?

Question

Sometimes I got warnings in Xilinx ISE:

Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

But if I use rising_edge() function, then there is no warning even if I have an incomplete case, like:

process (clk, rst)
begin   
    if (rst = '1') then
        test <= '0';
    elsif (rising_edge(clk)) then
        test <= '1';
    end if;
end process;

So why latches in FPGA are considered as an ugly design? And why using rising_edge() function can avoid those warnings? (In fact, I think using rising_edge() function will also introducing a latch)

Answer 1

Use of rising_edge(clk) results in an edge sensitive sequential design element, which is a flip-flop, and not a latch. A latch is made if the condition for state update is level sensitive, like en = '1'.

The FPGAs are optimized for implementation of synchronous design based on rising-edge sensitive flip-flops, and some FPGA technologies for example from Xilinx, limit resource utilization if latches are used. Also, it is typically more difficult to ensure correct timing constrains for latch based design.

So, use only latches if required for some specific reason, and in most designs, even large ones, there should be no latches at all.

Answer 2

In either case, (latch or register; without or with rising_edge(clk)) the incomplete IF or CASE indicates that storage is required, to hold the current value of the signal.

So the rising_edge(clk) function doesn't really change the logic of the circuit, it just cleans up its timings. Specifically it allows the synthesis tool to place a clocked register everywhere that would need a latch otherwise.

This is usually regarded as a good thing because clocked registers (flip-flops) are well supported in FPGA and most other technologies. They are building blocks with predictable timings essential for fast and reliable designs.

Latches ("transparent latches") have less reliable timings making timing analysis harder, so FPGAs don't usually support them so well, and their use is discouraged (though ASIC designers can, with a lot of care, use them successfully)

So rising_edge() doesn't exactly "avoid warnings" - it plants a safe register instead of a possibly unreliable latch, avoiding a potential timing problem.

Answer 3

Since your question has been already answered, I just want to add some considerations on the latch design.

Latches are not "ugly design", although if you read on basic internet sites, everybody seems to think the opposite. One of the greatest issues on latch design is that they cannot be implemented on FPGA, since FPGA has been designed to work with flip-flops. FPGAs are typically used to test code, and most designers don't like to write their code twice (one for FPGA and one for ASIC). Moreover latch design is more complex since you will need at least two clock phases (master-slave), but you can also have more phases. On the other hand, a good latch design can perform better than a FF design, especially for low power design: no need of fixing hold times, the transition time have less constraints, etc...

In any case one thing should be clear: if you're not an ASIC designer interested in low power techniques, you can live happy with only flip-flops.