Use of rising_edge(clk)
results in an edge sensitive sequential design element, which is a flip-flop, and not a latch. A latch is made if the condition for state update is level sensitive, like en = '1'
.
The FPGAs are optimized for implementation of synchronous design based on rising-edge sensitive flip-flops, and some FPGA technologies for example from Xilinx, limit resource utilization if latches are used. Also, it is typically more difficult to ensure correct timing constrains for latch based design.
So, use only latches if required for some specific reason, and in most designs, even large ones, there should be no latches at all.