VHDL Dual Port RAM unexpected latches generated

Question

I wrote a register file for my 16-bit MIPS architecture, here I make sure that my register0 contains all zeros, There are no syntax errors but I have some questions

1. Have I done the typecasting right? Because I get some warnings about latches being generated. What have I done wrong here?

2. Also what is the difference between conv_integer and to_integer(unsigned((w_addr))? Because when I used to_integer(unsigned(r_addr1)=0) I experienced errors.

   library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use IEEE.std_logic_unsigned.all;
   use IEEE.NUMERIC_STD.ALL;
   
   
   entity regfile is
   generic(
   N: integer:=4; --number of bits for address
   W: integer:=16 --number of bits
   );
    Port ( clk : in  STD_LOGIC;
      w_en : in  STD_LOGIC;
      r_addr1,r_addr2,w_addr : in  STD_LOGIC_VECTOR (N-1 downto 0);
      w_data: in STD_LOGIC_VECTOR (W-1 downto 0);
         r_data1, r_data2  : out  STD_LOGIC_VECTOR (W-1 downto 0));
   end regfile;
   
      architecture Behavioral of regfile is
      type regfile_type is array (W-1 downto 0) of STD_LOGIC_VECTOR (W-1 downto 0);
      signal RegisterFile: regfile_type;
      begin
      process(clk)
      begin
   if (clk = '1') then
       if (w_en = '1') then
           RegisterFile(to_integer(unsigned(w_addr))) <= w_data;
       end if;
   end if;
     end process;
        process (r_addr1, r_addr2)     
   begin
       if (conv_integer(r_addr1)=0) then
           r_data1 <= X"0000";
               else r_data1<=RegisterFile(to_integer(unsigned(r_addr1)));
       end if;
       if (conv_integer(r_addr2)=0) then 
           r_data2 <= X"0000";
               else r_data2 <= RegisterFile(to_integer(unsigned(r_addr2)));
       end if;
      end process;
       end Behavioral;
   

these are the warnings I am getting

WARNING:Xst:819 - "E:/Xilinx Projects/regfile/regfile.vhd" line 49: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:<w_en>, <w_data>
WARNING:Xst:819 - "E:/Xilinx Projects/regfile/regfile.vhd" line 58: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <RegisterFile>
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Answer 1

1. The line:

if (clk = '1') then

should be either:

if (clk'event and clk = '1') then

or:

if rising_edge(clk) then

This is where your latches are being created. While it may seem that the event should be implied by the sensitivity list, it needs to be explicit for the synthesis tool to properly infer a flip-flop.

2. to_integer(unsigned(r_addr1)=0) - did you mean to_integer(unsigned(r_addr1))=0 (which should work just fine)? Be careful to match your parentheses. Incidentally, unsigned compares just fine to integer literals, so you don't need the to_integer here. Just unsigned(r_addr1)=0 is fine.

Answer 2

Your clocked process isn't written correctly. The tools don't realize that clk is actually a clock. You need to either use clk'event or better yet use rising_edge(). The tools are creating a combinational process, rather than a sequential one. Since there's no else condition on the if statement, it makes your RegisterFile a latch. Here's some more information on what is a latch and how to avoid latches in your FPGA

process(clk)
begin
  if rising_edge(clk) then
    if w_en = '1' then
      RegisterFile(to_integer(unsigned(w_addr))) <= w_data;
    end if;
  end if;
end process;