1. The line:
if (clk = '1') then
should be either:
if (clk'event and clk = '1') then
or:
if rising_edge(clk) then
This is where your latches are being created. While it may seem that the event should be implied by the sensitivity list, it needs to be explicit for the synthesis tool to properly infer a flip-flop.
2. to_integer(unsigned(r_addr1)=0)
- did you mean to_integer(unsigned(r_addr1))=0
(which should work just fine)? Be careful to match your parentheses. Incidentally, unsigned
compares just fine to integer literals, so you don't need the to_integer
here. Just unsigned(r_addr1)=0
is fine.