getting "expecting a statement" on the line: "always @(negedge in2) begin"

Question

I keep getting the error:

...,NOTSTT (lab1.v,31|6): expecting a statement [9(IEEE)]

Can't I use negedge on signal that isn't clk ?
Can I use both poseedge on clk and negedge on in2 ?
The full code is:

module ex1 (in1, in2 ,clk , out1 , out2, bus);

//input&outputs
//==============
input  in1, in2, clk;
output out1,out2,bus;

//reg
//====
reg out1= 1'b0, out2=1'b0, y=1'b0 ;//y = previous state
reg [2:0] bus=3'b000;

//on clk pose edge
//=================
always @(posedge clk) begin 
    if ((in1==1)&&(y==0))
      out1 = 1;
    else if ((in1==0)&&(y==1))
      out2 = 1;
    else 
    begin
      out1 = 0;
      out2 = 0;
    end

    if (in1 == 1)
      y = 1'b1;
    else if (in1 == 0)
      y = 1'b0;

    always @(negedge in2) begin
      if(in1==1)
        bus = 3'b001;
      else if (in1==0)
        bus = 0;
      else
        bus <= bus + 1;
    end

endmodule

Answer 1

You missing a end for the first begin. It needs to be placed before always @(negedge in2). Every begin must have a corresponding end.

Also, use non-blocking(<=) assignments for synchronous logic.

I recommend you merge your always blocks with into one always @(posedge clock). It will eliminate the change of noise on in2 from generating unexpected behavior. Sample in2 to a new flop like you with in1.