You missing a end
for the first begin
. It needs to be placed before always @(negedge in2)
. Every begin
must have a corresponding end
.
Also, use non-blocking(<=
) assignments for synchronous logic.
I recommend you merge your always blocks with into one always @(posedge clock)
. It will eliminate the change of noise on in2
from generating unexpected behavior. Sample in2
to a new flop like you with in1
.