How to resolve this coding error

Question

Here is my code for writing two decimal numbers on 7 segment. I have used AN0 and AN1. I am getting this really weird error I don't know how to resolve it, is there any problem with my case structure? What does this error mean? any help would be appreciated

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity twosegments is
Port (  clk : in  STD_LOGIC;
            dig0: in std_logic_vector (3 downto 0);
            dig1: in STD_LOGIC_VECTOR (3 downto 0);
            segment : out  STD_LOGIC_VECTOR (6 downto 0);
            anode : out  STD_LOGIC_VECTOR (3 downto 0));
end twosegments;

architecture Behavioral of twosegments is

constant prescaler: STD_LOGIC_VECTOR(16 downto 0) := "00000000110010000";
signal prescaler_counter: STD_LOGIC_VECTOR(16 downto 0) := (others => '0');
signal sel: STD_LOGIC_VECTOR (1 downto 0);
signal r_anode: STD_LOGIC_VECTOR (3 downto 0);

begin
anode <= r_anode;

    process (clk) begin
        if (clk'event and clk = '1') then 
        prescaler_counter <= prescaler_counter + 1;
            if(prescaler_counter = prescaler) then
            sel <= sel+1;
            prescaler_counter <= (others => '0');
            end if;
        end if;
        end process;

    process (sel, dig0,dig1) begin
                case sel is 
                when "00" => r_anode <= "1110";
                when "01" => r_anode <= "1101";
                --when "10" => r_anode <= "1110";
                --when "11" => r_anode <= "1101";
                when others => r_anode <= "1111";
                end case;

                case r_anode is
                when "1110" => case "dig0" is
                                    when "0000"    => segment <= "0000001"; --0
                                    when "0001" => segment <= "1001111"; --1
                                    when "0010" => segment <= "0010010"; --2
                                    when "0011" => segment <= "0000110"; --3
                                    when "0100" => segment <= "1001100"; --4
                                    when "0101" => segment <= "0100100"; --5
                                    when "0110" => segment <= "0100000"; --6
                                    when "0111" => segment <= "0001111"; --7
                                    when "1000" => segment <= "0000000"; --8
                                    when "1001" => segment <= "0000100"; --9
                                    when others => segment <= "1111111";
                                    end case;
                when "1101" => case "dig1" is
                                    when "0000" => segment <= "0000001"; --0
                                    when "0001" => segment <= "1001111"; --1
                                    when "0010" => segment <= "0010010"; --2
                                    when "0011" => segment <= "0000110"; --3
                                    when "0100" => segment <= "1001100"; --4
                                    when "0101" => segment <= "0100100"; --5
                                    when "0110" => segment <= "0100000"; --6
                                    when "0111" => segment <= "0001111"; --7
                                    when "1000" => segment <= "0000000"; --8
                                    when "1001" => segment <= "0000100"; --9
                                    when others => segment <= "1111111"; --off
                                    end case;
                when others => segment <= "1111111";
                end case;
    end process;

 end Behavioral;

This is the weird error

 FATAL_ERROR:HDLParsers:vhpcstr.c:2040:$Id: vhpcstr.c,v 1.64 2008/12/03 00:28:13 sandeepd Exp $:200 - INTERNAL ERROR... while parsing "E:/Xilinx Projects/twosegs/twosegments.vhd" line 62. Contact your hot line.   Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Answer 1

There is a syntax error with quotes around dig0 and dig1 signal identifiers, so try to change case "dig0" is to case dig0 is, and case "dig1" is to case dig1 is.

But anyway, the Xilinx parser is not robust enough since it crashes, so it is a good habit to create a WebCase for issues like this, so Xilinx can improve in the future.

Answer 2

I would follow the error message directions. Specifically:

For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support