Export Xilinx ISE RTL/Technology Schematic into Netlist Text File

Question

I'm using VHDL on Xilinx ISE to generate a schematic of the register transfer logic in my project. I know ISE does a number of optimizations and gate reductions before spitting out the RTL and Technology schematics. What I want to do is to export the netlist of these schematics into some file so I can use that for my own program. Is there any way to do this? I keep reading about ngc files, but the contents of the ngc file generated upon synthesis make absolutely no sense.

Please let me know if you've done this before, I'd love to see how this is done. If it's not doable on ISE, can you recommend a tool that could do it?