Xilinx RLOC fails mapping

Question

I try to create a two level mux which contains two wide muxes. Each wide mux has 8 2-to-1 muxes which share the same select signals. Since I can use RLOC to pack one wide mux (= 8 2-to-1 muxes) which share the select signal into one Virtex-5 slice. I want to pack these two wide muxes into 2 slices. But the following code gives me a map error: ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset, RLOC=X2Y2)

Anyone know how to solve this?

module mux_8(a, c, d, sel, o);
input [7:0] a;
input [7:0] d;
input [7:0] c;
input [1:0] sel;
output [7:0] o;

wire [7:0] b;

(* RLOC = "X0Y0" *)
mux mux_0(.a(a[0]), .b(b[0]), .sel(sel[0]), .o(o[0]));
(* RLOC = "X0Y0" *)
mux mux_1(.a(a[1]), .b(b[1]), .sel(sel[0]), .o(o[1]));
(* RLOC = "X0Y0" *)
mux mux_2(.a(a[2]), .b(b[2]), .sel(sel[0]), .o(o[2]));
(* RLOC = "X0Y0" *)
mux mux_3(.a(a[3]), .b(b[3]), .sel(sel[0]), .o(o[3]));
(* RLOC = "X0Y0" *)
mux mux_4(.a(a[4]), .b(b[4]), .sel(sel[0]), .o(o[4]));
(* RLOC = "X0Y0" *)
mux mux_5(.a(a[5]), .b(b[5]), .sel(sel[0]), .o(o[5]));
(* RLOC = "X0Y0" *)
mux mux_6(.a(a[6]), .b(b[6]), .sel(sel[0]), .o(o[6]));
(* RLOC = "X0Y0" *)
mux mux_7(.a(a[7]), .b(b[7]), .sel(sel[0]), .o(o[7]));

(* RLOC = "X2Y2" *)
mux mux_8 (.a(c[0]), .b(d[0]), .sel(sel[1]), .o(b[0]));
(* RLOC = "X2Y2" *)
mux mux_9 (.a(c[1]), .b(d[1]), .sel(sel[1]), .o(b[1]));
(* RLOC = "X2Y2" *)
mux mux_10(.a(c[2]), .b(d[2]), .sel(sel[1]), .o(b[2]));
(* RLOC = "X2Y2" *)
mux mux_11(.a(c[3]), .b(d[3]), .sel(sel[1]), .o(b[3]));
(* RLOC = "X2Y2" *)
mux mux_12(.a(c[4]), .b(d[4]), .sel(sel[1]), .o(b[4]));
(* RLOC = "X2Y2" *)
mux mux_13(.a(c[5]), .b(d[5]), .sel(sel[1]), .o(b[5]));
(* RLOC = "X2Y2" *)
mux mux_14(.a(c[6]), .b(d[6]), .sel(sel[1]), .o(b[6]));
(* RLOC = "X2Y2" *)
mux mux_15(.a(c[7]), .b(d[7]), .sel(sel[1]), .o(b[7]));

endmodule


(* LUT_MAP = "yes" *) 
module mux(a, b, sel, o);
input a;
input b;
input sel;
output o;

assign o = (~sel & a) | (sel & b);
endmodule

Answer 1

I am afraid it is reporting it is impossible to route according to your constraint. You can use fpgaeditor (a tool in ISE) to see the routing resources of the target slice. You can try to route it manually in fpgaeditor. If it is possible, you can save the routed design as a hard-marco and use the marco in your design. However, I believe you have put too many mux in one slice, which causes routing congestion that can not be handled.