Xilinx rloc échoue la cartographie

Question

J'essaie de créer un MUX de deux niveaux qui contient deux muxes larges.Chaque MUX large dispose de 8 muxes de 2 à 1 partageant les mêmes signaux de sélection.Étant donné que je peux utiliser RLOC pour emballer une large mux (= 8 muxes de 2 à 1) qui partagent le signal de sélection dans une tranche Virex-5.Je veux emballer ces deux grands muxques en 2 tranches. Mais le code suivant me donne une erreur cartographique: Erreur: Pack: 679 - Impossible d'obéir des contraintes de conception (Macroname= HSt, RLoc= X2Y2)

Quelqu'un sache comment résoudre ce problème?

module mux_8(a, c, d, sel, o);
input [7:0] a;
input [7:0] d;
input [7:0] c;
input [1:0] sel;
output [7:0] o;

wire [7:0] b;

(* RLOC = "X0Y0" *)
mux mux_0(.a(a[0]), .b(b[0]), .sel(sel[0]), .o(o[0]));
(* RLOC = "X0Y0" *)
mux mux_1(.a(a[1]), .b(b[1]), .sel(sel[0]), .o(o[1]));
(* RLOC = "X0Y0" *)
mux mux_2(.a(a[2]), .b(b[2]), .sel(sel[0]), .o(o[2]));
(* RLOC = "X0Y0" *)
mux mux_3(.a(a[3]), .b(b[3]), .sel(sel[0]), .o(o[3]));
(* RLOC = "X0Y0" *)
mux mux_4(.a(a[4]), .b(b[4]), .sel(sel[0]), .o(o[4]));
(* RLOC = "X0Y0" *)
mux mux_5(.a(a[5]), .b(b[5]), .sel(sel[0]), .o(o[5]));
(* RLOC = "X0Y0" *)
mux mux_6(.a(a[6]), .b(b[6]), .sel(sel[0]), .o(o[6]));
(* RLOC = "X0Y0" *)
mux mux_7(.a(a[7]), .b(b[7]), .sel(sel[0]), .o(o[7]));

(* RLOC = "X2Y2" *)
mux mux_8 (.a(c[0]), .b(d[0]), .sel(sel[1]), .o(b[0]));
(* RLOC = "X2Y2" *)
mux mux_9 (.a(c[1]), .b(d[1]), .sel(sel[1]), .o(b[1]));
(* RLOC = "X2Y2" *)
mux mux_10(.a(c[2]), .b(d[2]), .sel(sel[1]), .o(b[2]));
(* RLOC = "X2Y2" *)
mux mux_11(.a(c[3]), .b(d[3]), .sel(sel[1]), .o(b[3]));
(* RLOC = "X2Y2" *)
mux mux_12(.a(c[4]), .b(d[4]), .sel(sel[1]), .o(b[4]));
(* RLOC = "X2Y2" *)
mux mux_13(.a(c[5]), .b(d[5]), .sel(sel[1]), .o(b[5]));
(* RLOC = "X2Y2" *)
mux mux_14(.a(c[6]), .b(d[6]), .sel(sel[1]), .o(b[6]));
(* RLOC = "X2Y2" *)
mux mux_15(.a(c[7]), .b(d[7]), .sel(sel[1]), .o(b[7]));

endmodule


(* LUT_MAP = "yes" *) 
module mux(a, b, sel, o);
input a;
input b;
input sel;
output o;

assign o = (~sel & a) | (sel & b);
endmodule

Answer 1

I am afraid it is reporting it is impossible to route according to your constraint. You can use fpgaeditor (a tool in ISE) to see the routing resources of the target slice. You can try to route it manually in fpgaeditor. If it is possible, you can save the routed design as a hard-marco and use the marco in your design. However, I believe you have put too many mux in one slice, which causes routing congestion that can not be handled.