How to implement data structures like stack/queue in VHDL?

Question

How can I simulate the behavior of a stack or a queue in VHDL? Any pointers?

I had thought of using some thing like logical shift operation of bits but how to check the constraints of stack being empty or the case of stack overflow?

Answer 1

You can start by reading Peter Ashenden book "The Designer's Guide to VHDL". On chapter 19 he implements a Queuing Network and he goes at length to explain how to implement queues on VHDL. You can get the VHDL files for that book at: http://www.csee.umbc.edu/help/VHDL/ashenden/ch_19/

Answer 2

You will want to implement a FIFO if you are working in VHDL/Verilog. If this is going to be instantiated in an actual FPGA, you will model the FIFO with read and write pointers to block ram in the FPGA. Check out a well-developed implementation at OpenCores...

http://opencores.org/project,versatile_fifo

Answer 3

Don't implement a stack. Use the FPGA vendor's core.

Answer 4

you can make a RAM Component and use it as FIFO, LIFO or every kind of data structure you want.

if you need a Stack, after making RAM Component don't use Address bus for it, make a variable which contain Top Of Stack address. then with POP decrease it (first send the output to Data Bus) and with PUSH increase it (then save the input to TOS[top of stack] Variable).

if you need more I can tell you more...