Does RAM get an indication of data size required

Question

Pre-information:

I'm sure someone has asked something along these lines, but no matter how I word it, I can't seem to find a definitive answer

Question:

Does RAM get some kind of indication as to how much data the CPU requires or is there a set amount of data and if the CPU needs more, it needs to call again (and what is that set amount of data).

During a cache miss, the CPU will require at least a single cache line (32, 64 or 128 bytes). Does the CPU need to query RAM multiple times to get a single cache line (assuming the set amount is 8 bytes) or does the RAM return more data per call or does RAM have some way of being notified as to how much data is required?

I'm aware the CPU is most likely going to call more than just a single cache line to avoid the lengthy request from RAM if more data is needed in future from the same block of memory.

Extra Points:

If you do know and have more information, the following extras would also interest me:

• If this is different depending on CPU make (generational differences can also be interesting but if you do add information about that, please skip similar generations)
• If this is different depending on RAM type
• How the CPU can request a different sized cache line or block size (only applies if RAM returns a fixed size that's the size of a block or cache line)
• Any other useful relevant information or resources for further reading

Potential answer:

I seem to have found a clue to the answer when looking at the transfer rate of RAM, specifically where it indicates how to calculate the transfer rate from the specifications and from "DDR SDRAM prefetch architecture" which indicates how many 64 bit "blocks" can be requested per call to RAM (e.g. 8 for DDR3 and DDR4, 4 for DDR2 and 2 for DDR1)

Answer 1

In most modern hardware, main memory is more like a peripheral.

What I'm going to describe in what follows is Intel-esque PC-ish hardware, but it's very similar on other systems.

During initial booting, when the power is first applied, the CPU only has cache, firmware, and some memory-mapped I/O. One of the first jobs is to initialise an external piece of hardware traditionally known as the "memory controller" or "memory controller hub" (in PC hardware it's part of the northbridge), which communicates directly with RAM modules.

I say "RAM modules", because they are really like peripherals, as I said. The hardware asks the module how much memory is present, and also negotiate the details of the protocol they will use to transfer data to and from main memory.

Like other modern peripherals, modern RAM modules can burst reads and writes, that is, they can read and write a larger "block" of memory using one transfer operation. So even if the "last" level of cache operates with the same cache line size as lower-level caches, it can transfer larger blocks of data to and from RAM than that.

This is a useful optimisation when performing operations like linear scans through a block of memory. Some combination of the CPU and cache controllers can detect this, and use that information to issue a prefetch from RAM.

Answer 2

RAM just gets requests for data to move to/from the CPU (really the MMU). Data is moved in units of cache lines.

Answer 3

Currently, cache sizes are usually so big that more than one transfer from RAM to cache is needed to completely load a cache line. But reading from RAM takes time for the RAM to receive the address of the data to be read, and then time for the actual transfer, and asking RAM to perform say four transfers in a row is much faster than accessing four random memory locations.

Some processors have a feature that allows them to tell RAM in which order to transfer different parts of a cache line. Say there are four transfers needed to fill a cache line, then you would like to load the quarter cache line first that is actually needed (and then fill the rest).

It would be possible to only partially fill a cache line (and proceed filling a different cache line instead of completely filling the first one).