Fast Saturate and shift two Halfwords in ARM asm

Question

I have two signed 16-bit values in a 32-bit word, and I need to shift them right (divide) on constant value (it can be from 1 to 6) and saturate to byte (0..0xFF).

For example,

• 0x FFE1 00AA with shift=5 must become 0x 0000 0005;
• 0x 2345 1234 must become 0x 00FF 0091

I'm trying to saturate the values simultaneously, something like this pseudo-code:

AND RT, R0, 0x80008000; - mask high bits to get negatives
ORR RT, RT, LSR #1
ORR RT, RT, LSR #2
ORR RT, RT, LSR #4
ORR RT, RT, LSR #8; - now its expanded signs in each halfword
MVN RT, RT
AND R0, RT; now negative values are zero
; here something to saturate high overflow and shift after

but code I get is very ugly and slow. :) The best (fastest) thing I have now is separate saturation of each half, like this:

MOV RT, R0, LSL #16
MOVS RT, RT, ASR #16+5
MOVMI RT, #0
CMP RT, RT, #256
MOVCS RT, #255
MOVS R0, R0, ASR #16+5
MOVMI R0, #0
CMP R0, R0, #256
MOVCS R0, #255
ORR R0, RT, R0, LSL #16

But it's 10 cycles. :( Can it be faster?

p.s.: Later I found USAT16 instruction for this, but it's only for ARMv6. And I need code to work on ARMv5TE and ARMv4.

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Edit: now I rewrite my first code:

ANDS RT, 0x10000, R0 << 1;      // 0x10000 is in register. Sign (HI) moves to C flag, Sign (LO) is masked
SUBNE RT, RT, 1;            // Mask LO with 0xFFFF if it's negative
SUBCS RT, RT, 0x10000;      // Mask HI with 0xFFFF if it's negative
BIC R0, R0, RT;         // Negatives are 0 now. The mask can be used as XOR too
TST R0, 0xE0000000;         // check HI overflow             
ORRNE R0, R0, 0x1FE00000        // set HI to 0xFF (shifted) if so
TST R0, 0x0000E000          // check LO overflow             
ORRNE R0, R0, 0x00001FE0        // set LO to 0xFF if so          
AND R0, 0x00FF00FF, R0 >> 5;    // 0x00FF00FF is in register     

but it isn't beautiful.

Answer 1

It was a good idea to use one check to set flags for two operations. But I can't do it for second part. I can do something else :) Here is universal variant to use with any shift from 1 to 6:

;prepare:
MOV RMask, ((0xFF00 << shift) & 0xFF00) << 16;  Mask overflow bits
MOV R_0xFF00FF, 0xFF;
ORR R_0xFF00FF, 0xFF000000;
;...
; innerloop:
;....
TST R0, RMask, R0 << 16;            Set flags for LO half
ORRNE R0, R0, 0xFF << shift;        It is overflow. First try positive
BICMI R0, R0, 0xFF << shift;        Fix it if negative. LO half is ready
TST R0, RMask, R0;              Set flags for HI half. Can TST R0, R0, #Mask also
ORRNE R0, R0, 0xFF << (shift+16)
BICNE R0, R0, 0xFF << (shift+16)
AND R0, R_0xFF00FF, R0 >> shift;        Shift and mask

So it's 7 cycles now. :)

Can it be better?

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Edit: looks like overflows are rare enough, so it's a good idea to add something like this:

TST R0, 0xE000E000
BEQ no_saturation_needed
... ; saturation ops here

Answer 2

What you have is about as good as you're going to do for the problem as stated. If you're doing this for a lot of data in a tight loop, and can afford a few registers to hold masks, you may be able to save a cycle or two, but it's not going to be a big improvement. There just isn't great support for this type of "small-vector" saturation operation on ARM before the v6 architecture.

Basically, unless this is the only bottleneck in your program, it's time to put this away and move on to the next hotspot.