HDL sythesis complains about missing signals in sensitivity list

Question

Hello I've got this simple VHDL process (Generated from MyHDL code):

DIGIPOT_CONTROLLER_CONNECTCLOCK: process (delayedClock) is
begin
    if to_boolean(clkEn) then
        if to_boolean(delayedClock) then
            scl_d <= '0';
        else
            scl_d <= 'Z';
        end if;
    else
        if to_boolean(sclIdleValue) then
            scl_d <= 'Z';
        else
            scl_d <= '0';
        end if;
    end if;
end process DIGIPOT_CONTROLLER_CONNECTCLOCK;

Original MyHDL code:

@always(delayedClock)
def connectClock():
    if(clkEn):
        if(delayedClock):
            scl_d.next = False
        else:
            scl_d.next = None
    else:
        if(sclIdleValue):
            scl_d.next = None
        else:
            scl_d.next = False

In simulation it works perfectly(both ISIM and MyHDL simulator), but when I try to synthesise it into Spartan 6 it gives these warnings: clken should be on the sensitivity list of the process sclidlevalue should be on the sensitivity list of the process

Which I understand that it somehow inferred that this process should be sensitive on clkEn and sclIdleValue signals. But of course this is not what I have intended. I want it to change output only when delayedClock changes it's state, not when clkEn or sclIdleValue changes their respective states.

Is it something that could not be done in Spartan 6 architecture? Or should I decribe process otherwise to have my intended behavior?

Answer 1

I have finally figured it out this is resulting MyHDL code:

@always(delayedClock.posedge, reset.posedge)
def connectClock():
    if(reset == 1):
        delayedClock_int.next = True
    else:
        delayedClock_int.next = not delayedClock_int
        if(clkEn):
            if(delayedClock_int):
                scl_d.next = False
            else:
                scl_d.next = None
        else:
            if(sclIdleValue):
                scl_d.next = None
            else:
                scl_d.next = False

and (generated) VHDL:

DIGIPOT_CONTROLLER_CONNECTCLOCK: process (delayedClock, reset) is
begin
    if (reset = '1') then
        delayedClock_int <= '1';
    elsif rising_edge(delayedClock) then
        delayedClock_int <= to_std_logic((not to_boolean(delayedClock_int)));
        if to_boolean(clkEn) then
            if to_boolean(delayedClock_int) then
                scl_d <= '0';
            else
                scl_d <= 'Z';
            end if;
        else
            if to_boolean(sclIdleValue) then
                scl_d <= 'Z';
            else
                scl_d <= '0';
            end if;
        end if;
    end if;
end process DIGIPOT_CONTROLLER_CONNECTCLOCK;

I had to make delayed clock twice the frequency (and then divide it by two in my connectClock process), this way it produces the same result as original process and it is sythesisable without warning.. the reason for phased out clock is SCL of I2C waveform as shown here: