I have finally figured it out this is resulting MyHDL code:
@always(delayedClock.posedge, reset.posedge)
def connectClock():
if(reset == 1):
delayedClock_int.next = True
else:
delayedClock_int.next = not delayedClock_int
if(clkEn):
if(delayedClock_int):
scl_d.next = False
else:
scl_d.next = None
else:
if(sclIdleValue):
scl_d.next = None
else:
scl_d.next = False
and (generated) VHDL:
DIGIPOT_CONTROLLER_CONNECTCLOCK: process (delayedClock, reset) is
begin
if (reset = '1') then
delayedClock_int <= '1';
elsif rising_edge(delayedClock) then
delayedClock_int <= to_std_logic((not to_boolean(delayedClock_int)));
if to_boolean(clkEn) then
if to_boolean(delayedClock_int) then
scl_d <= '0';
else
scl_d <= 'Z';
end if;
else
if to_boolean(sclIdleValue) then
scl_d <= 'Z';
else
scl_d <= '0';
end if;
end if;
end if;
end process DIGIPOT_CONTROLLER_CONNECTCLOCK;
I had to make delayed clock twice the frequency (and then divide it by two in my connectClock process), this way it produces the same result as original process and it is sythesisable without warning.. the reason for phased out clock is SCL of I2C waveform as shown here: