Fundamental Verilog Concepts

Question

I have my first verilog assignment due in a few days and for whatever reason these concepts are escaping me. I don't think I'm thinking in terms of parallelism and hardware or something.

My question is that I have to and a few switches and buttons together using wires and turn on 3 LEDs in array of 7. I'm pretty sure I know how to do the computational logic, but I can't figure out how to use assign and wire to properly turn on all 3 LEDs without writing 3 separate lines. It feels wrong to do:

assign Led[0] = output;
assign Led[1] = output;
assign Led[2] = output;

Also, it's weird because there are 7 LEDs on the board and I'm picking on LEDs 0,2,4.

Can someone walk me through how this is supposed to work the proper way? We don't have a textbook and I've been reading the basics online, but I just can't seem to figure out how this is supposed to work. Thanks!

Edit: This is my current code, but I am getting errors that say nothing is "driven". What gives?

module Lab2_1(input [5:0] sw, input btns, output [7:0] Led );

    wire [2:0] leds; 
    wand out; 

    assign leds = {Led[0], Led[2], Led[4]};

    and U1   (out, sw[0], sw[1]);
    and U2   (out,~sw[2],~sw[3]);
    xor U3   (out,sw[4],sw[5]);
    assign   out = btns;
    assign leds[2:0] = {3{out}};

endmodule

Errors:

ERROR:PhysDesignRules:368 - The signal <Led<3>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<4>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<5>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<6>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<7>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<0>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<1>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal <Led<2>_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
ERROR:PhysDesignRules:10 - The network <Led<3>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<4>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<5>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<6>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<7>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<0>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<1>_OBUF> is completely unrouted.
ERROR:PhysDesignRules:10 - The network <Led<2>_OBUF> is completely unrouted.
ERROR:Bitgen:25 - DRC detected 16 errors and 0 warnings.  Please see the
   previously displayed individual error or warning messages for more details.

Answer 1

What you have already seems perfectly fine, though if you wanted to do it in one line you could use a concatenation and or replication operators to assign multiple bits of Led. Both these statements are equivalent to your code sample:

assign Led[2:0] = {output, output, output};

or

assign Led[2:0] = {3{output}};

I don't know if these are any better or more proper than what you already have, but just writing them to show some examples of what is possible to do.

=== EDIT ===

You're getting errors because you're not driving any of the bits of Led.

1. This looks backward: assign leds = {Led[0], Led[2], Led[4]};
Led is the output of the module, so it should be assigned to, meaning it should be on the left hand side of the equal, so I would guess this should look like assign {Led[0], Led[2], Led[4]} = leds;

2. Your module has an 8-bit Led output, but you're only assigning 3 bits of it. You should assign the other 5 bits to either constant 1 or 0.