U0
is instance name of the counter
module, defined in http://www.asic-world.com/verilog/art_testbench_writing1.html.
So, you should check the definition of counter module. When you want to use the module, you are instantiating it. There can be many instantiations of any module, so instantiations are named. Syntax is:
<modulename> <instancename> ( <connections> )
Check examples, e.g. in http://web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/verilog_modules.pdf