What is u0 in verilog? [duplicate]

Question

This question already has answers here:

Verilog: How to instantiate a module (3 answers)

Closed last year.

I was looking at this tutorial on Verilog, and the author uses something like

module counter_tb;
  reg clk, reset, enable; 
  wire [3:0] count; 

  counter U0 ( 
  .clk    (clk), 
  .reset  (reset), 
  .enable (enable), 
  .count  (count) 
  ); 

endmodule 

What is U0? He does not mention it earlier in the tutorial anywhere.

Answer 1

U0 is instance name of the counter module, defined in http://www.asic-world.com/verilog/art_testbench_writing1.html.

So, you should check the definition of counter module. When you want to use the module, you are instantiating it. There can be many instantiations of any module, so instantiations are named. Syntax is:

 <modulename> <instancename> ( <connections> )

Check examples, e.g. in http://web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/verilog_modules.pdf

Answer 2

This is an older question; however, I was perusing the same tutorial and had the same question. I thought I would give a more detailed explanation of the anatomy of the instantiation.

[moduleName] [instanceName] ( [connections] );

The name of the module to instantiate is followed by the name of the instance. This is then followed by a parenthesized list of connections, comma-separated, with the following syntax:

.[pin] ( [connectionName] ),

Where [pin] is the name of the output/input in the original module definition and [connectionName] is how the testbench will refer to that connection.
The pin name and the connection name do not have to match, though many examples I've seen use the pin name as the connection name.

Source on slide 12 of (Updated link originally provided in @osgx's answer): Verilog_Modules.pdf