Is the system verilog constuct do-while synthesizable?

Question

Is the construct do <blah> while (0) synthesizable in system verilog?

I ask because I have some complex macros that I wish to protect using this syntax.

e.g.

`define my_macro(arg1) \
    do \
         my_reg <= arg1; \
         valid <= 1; \
    while (0)

Or is there a similar verilog construct that I can use. Verilog would be preferred as it is used by more tools.

Answer 1

The loop construct in SystemVerilog, such as for, while, do...while, repeat, can be synthesized in modern logic synthesizer if and only if the condition expression can be unrolled and calculated during elaboration (or compilation time). It is not a problem to the tool, because the tool just employes loop unrolling techniques from compilers. By this way, the condition expression have to be calculated during the compilation time (means cannot dynamically change in the runtime) to determine what the termination condition of a loop is.

Sometimes even if the loop have a termination condition, but the tool may have some restrictions to limit the loop unrolling not exceeds a threshold, such as 1k or 10k, to prevent wasting much time in unrolling and expanding the loop body (tools does not know the limitation, it just keeps trying and testing the termination condition)

In following example, the loop can be synthesized.

for (i=0; i < 10; i=i+1)
for (i=0; i < WIDTH; i=i+1)  // if WIDTH is a constant, or a parameter

for (i=0; i < 10; i=i+1) begin
  ...
  if (i > 5) break;          // `continue' and `break' are also supported if the loop
                             // follows the synthesizable rules.
  ...
end

Answer 2

Just wanting to expand on what I said in a comment in reply to this:

What's wrong with begin and end? – Paul S yesterday

@PaulS: because then my_macro(1); expands to begin end; and that trailing semicolon is a syntax error. And how does the person who called my macro know whether it's a single statement or a multi-statement one? (or it might even change ...) – dave yesterday

The UVM library uses the following idiom extensively:

`define uvm_info(ID,MSG,VERBOSITY) \
   begin \
     if (uvm_report_enabled(VERBOSITY,UVM_INFO,ID)) \
       uvm_report_info (ID, MSG, VERBOSITY, `uvm_file, `uvm_line); \
   end

I've never had IES report a syntax error because I put a trailing semicolon on that macro, and I'm pretty sure I do it a lot. Granted I can't find in the spec if it should be a syntax error or not, but I think it gets interpreted as a null statement.

Regardless, I think it's probably a good rule to say that if my_macro is a single statement it should include its ;. Then single statement and multi statement macros work in the same way.

Answer 3

no its not....better use begin....end

Answer 4

@dave, you can try this:

`define my_macro(arg1) \
  if (1) \
    my_reg <= arg1; \
    valid <= 1; \
  else

In any language using an 'if...else' wouldn't be more inefficient that using a 'do...while' so the former is preferred. Here is a link to the C++ FAQ-lite illustrating a similar construction. Also using 'if...else' makes it a Verilog-1995 as opposed to a SystemVerilog construct.

BTW @Paul S, you can get a syntax error on putting a ';' after the macro, in code like this:

if (foo)
  `uvm_info (get_type_name(), "foo", UVM_DEBUG);
else
  `uvm_info (get_type_name(), "not foo", UVM_DEBUG);

I am not sure why UVM chose to do this instead of following what has been done for ages in the SW world... use 'do...while()' or 'if...else' to allow macro users to put that semicolon. May be unlike in C/C++, in Verilog/SV macros are visibly different from tasks due to the '`' so UVM expects users of the macros not to have a ';' at the end?