The loop construct in SystemVerilog, such as for, while, do...while, repeat, can be synthesized in modern logic synthesizer if and only if the condition expression can be unrolled and calculated during elaboration (or compilation time). It is not a problem to the tool, because the tool just employes loop unrolling techniques from compilers. By this way, the condition expression have to be calculated during the compilation time (means cannot dynamically change in the runtime) to determine what the termination condition of a loop is.
Sometimes even if the loop have a termination condition, but the tool may have some restrictions to limit the loop unrolling not exceeds a threshold, such as 1k or 10k, to prevent wasting much time in unrolling and expanding the loop body (tools does not know the limitation, it just keeps trying and testing the termination condition)
In following example, the loop can be synthesized.
for (i=0; i < 10; i=i+1)
for (i=0; i < WIDTH; i=i+1) // if WIDTH is a constant, or a parameter
for (i=0; i < 10; i=i+1) begin
...
if (i > 5) break; // `continue' and `break' are also supported if the loop
// follows the synthesizable rules.
...
end