If you wanted, you could make a record with strings to 'wrap' around your actual signal. This is a little kludgey, but it is hard for me to think of another way, short of head-hurting magic with files that would be even worse in VHDL. So:
type stdWithName is
record
name : String;
value : std_logic;
end record;
you could then initialize this like:
signal val : std_logic := '0';
signal withName : stdWithName := ("withName",val);
and compare the name like
if (withName.name = "withName") then
-- huzzah! a match.
end if;