Understanding a simple VHDL process

Question

Here is some VHDL code I am given for reading and writing to a memory address that I am trying to understand. The basic idea is that if we have a rising clock edge and write is enabled (we = '1'), then we modify the array called ram and store data inside. Then we assign the address from which we just read to addr_reg, and then outside the process we assign the contents of ram at address addr_reg to q for reading output.

process(clk) begin
    if(rising_edge(clk)) then
        if(we = '1') then
            ram(addr) <= data;
        end if;
        -- Register the address for reading
        addr_reg <= addr;
    end if;
end process;

q <= ram(addr_reg);

In this case, is the process "slower" than the hardcoded line q <= ram(addr_reg);? In other words, are we reading the previous value at addr_reg while simultaneously writing a new value to addr such that on the next clock edge that value will be read? Or is the hardcoded line q <= ram(addr_reg); fired after addr_reg is assigned in the process, so we are reading the value that we just wrote, namely data?

For a complete answer, I'm looking for a detailed explanation of the timeline of events for this code with respect to the clock.

Answer 1

On rising_edge(clk) both ram and addr_reg are updated with the new contents. The effect of this updated contents is visible right after (a delta cycle) the rising edge of clk through the combinatorial q <= ram(addr_reg), which will shown the new values immediately.

So you are reading the value that we just wrote, namely data. The signals for this case are shown below.