How would you implement this digital logic in Verilog or VHDL?
Question
I posted an answer to another stackoverflow question which requires some digital logic to be implemented in Verilog or VHDL so that it can be programmed into an FPGA.
How would you implement the following logic diagram in Verilog, VHDL, or any other hardware description language?
The numbered boxes represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read back into that same computer system.
alt text http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg
See also: this stackoverflow question
Solution
Something like this?
module scheduler
#( parameter K = 10 )
(
input wire [K:1] current,
input wire [K:1] mask,
output reg [K:1] next
);
reg [K:1] a;
reg [K:1] b;
//'[i+1]' busses that wrap.
// eg, for a 4-bit bus...
// a[i]: a[4],a[3],a[2],a[1] (obviously...)
// a_wrap[i]: a[1],a[4],a[3],a[2]
wire [K:1] mask_wrap = { mask[1],mask[K:2] };
wire [K:1] a_wrap = { a[1], a[K:2] };
wire [K:1] current_wrap = { current[1], current[K:2] };
integer i;
always @( * ) begin
for( i=1; i<=K; i=i+1 ) begin
a[i] = ~current_wrap[i] && b[i];
b[i] = a_wrap[i] || mask_wrap[i];
next[i] = ~a[i] && mask_wrap[i];
end
end
endmodule
(Disclaimer: linted but not simulated)
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