Question

I just recently upgraded to Modelsim 10 and when I recompiled all my code, only 30 out of 37 compiled. Those that wouldn't compile had a common error

No feasible entries for infix operator "&"

I simply included the packages for std_logic, change bits to std_logics, and it magically fixes the problem on the first recompiling (a rare sight for me). My question is what is why did the new compiler (if it even is new) not accept bit & unsigned(N downto 0). Is it some kind of new standard to force HDL coders to use more abstraction? I saw a similar question which solved my problem, but I want to know why the compilation is suddenly different.

Was it helpful?

Solution

Could it be that your new ModelSim uses different default settings (e.g. -2008 instead of -87)?

OTHER TIPS

For set old version of VHDL, you should change it in file modelsim.ini (it has various parameter):

[vcom]
; VHDL93 variable selects language version as the default. 
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Value of 3 or 2008 for VHDL-2008
VHDL93 = ????
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