Booth encode not working, simulation included

Question

I am writing a Booth encode for array multiplier. This is one of the module:

module add_input (M,pos,neg,C);
parameter n=8;

input  [n-1:0]M;
input  pos,neg;

output [2*n-1:0]C;
reg [2*n-1:0]C;

integer k;

always @ (*)
begin
 for (k=0;k<=n-1;k=k+1)
 begin
   C[k]=(pos& (M[k]))|((~M[k])&neg);
 end
   C[2*n-1:n]={n{C[n-1]}};
end

endmodule

The testbench simulation for this module is ok:

a busy cat http://img39.imageshack.us/img39/3444/74546414.jpg !

However, when I put this module into the top-level design, I can't see any output from module add_input. Really wondering why, been debugging this for whole night.

Code:

module Array_Mutiplier (M,Q,outcome, t_pos, t_neg,t_Y1);
parameter n=8;
parameter m=16;
input [n-1:0]M,Q;
output [m-1:0]outcome;

//-----------------------------------------------------------
output [n-1:0] t_pos, t_neg;
output [m-1:0] t_Y1;
//-----------------------------------------------------------
//first part, got the booth code
wire [n-1:0]negative,positive;
booth_encode BE(Q,positive,negative);

//get the Y for the full adder
wire [m-1:0]Y1;
add_input row_1 (M,positive[0],negative[0],Y1);
wire [2*n-1:0]Y2;
add_input row_2 (M,positive[1],negative[1],Y2);
wire [2*n-1:0]Y3;
add_input row_3 (M,positive[2],negative[2],Y3);
wire [2*n-1:0]Y4;
add_input row_4 (M,positive[3],negative[3],Y4);
wire [2*n-1:0]Y5;
add_input row_5 (M,positive[4],negative[4],Y5);
wire [2*n-1:0]Y6;
add_input row_6 (M,positive[5],negative[5],Y6);
wire [2*n-1:0]Y7;
add_input row_7 (M,positive[6],negative[6],Y7);
wire [2*n-1:0]Y8;
add_input row_8 (M,positive[7],negative[7],Y8);


assign t_pos=positive;
assign t_neg=negative;
assign t_Y1=Y1;

endmodule

a busy cat http://img855.imageshack.us/img855/3361/28395154.png !

Based on the simulation you can see the booth encoder is working properly, but why output t_Y1 is always 0?

Answer 1

From your 2nd waveform, t_pos[0] and t_neg[0] are both zero, which means that positive[0] and negative[0] are both zero as well. Inside your row_1 instance, pos and neg are zero, which means that all bits of C[7:0] are zero ((pos& (M[k]))|((~M[k])&neg) evaluates to 0). Since C[7]=0, this means C[15:8]=0, and therefore C[15:0]=0 and Y1 and t_Y1 are also zero.