Why IEEE vhdl standard library is not STL?

Question

IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator.

It seems that Altera's MAX+Plus II do not support AND2, INV component(if there are,please feel free to correct me),but Xilinx Foundation does.

Why IEEE vhdl standard library could not become something like STL in the C++ world?

thanks.

Answer 1

Invert, And, Or,... for std_logic types are supported by IEEE libraries:

a <= b and c
d <= not e
f <= g or h

Your synthesis tool will automatically translate these expressions to the best implementation for your target technology (Xilinx FPGA, Altera FPGA, ASIC, ...). There is no need to explicitly instantiate technology specific components. Instantiating technology specific components might even obstruct optimizations.

You should always try to write your VHDL code technology independent. This allows you to reuse code.

Answer 2

The "components" you are asking for are operators in VHDL.

You can also directly instantiate things like AND2 and INV components, but you will need to build these libraries (or use libraries provided for you).

Answer 3

Because fpga design software is high related to the targeted chip and there are only two enterprise capable to develop such software.Altera's Max+PlusII could only support chips ship from Altera,so does Xilinx.These vendor control the whole progress of fpga design,from software to hardware.Then they tends to develop specific feature targeted on they own platform.So IEEE standard library could not be something like STL in the C++ world.

AND2 is primitive of Altera Max+PlusII,but it is not primitive of Xilinx Webpack.Actually we could desing our own component AND2(which Xilinx choose to provide it within unisim package,but we choose not to load thi package).

INV is not primitive of Altera Max+PlusII,neither Xilinx WebPack.