What is the difference between == and === in Verilog?

StackOverflow https://stackoverflow.com/questions/5927615

  •  30-10-2019
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문제

What is the difference between:

if (dataoutput[7:0] == 8'bx) begin

and

if (dataoutput[7:0] === 8'bx) begin

After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)

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